The Josephson transmission line (JTL), already briefly discussed in the
previous section (Fig. 
) is probably the simplest and most
ubiquitous RSFQ cell. A ``real-life'' schematic of a two-stage JTL is
shown in Fig.
Operation of the device is extremely simple: SFQ pulses are
transferred from left to right with a delay of approximately 10 ps
(for HYPRES' 1-kA technology [7]). This circuit (as well
as all the RSFQ cells) was extensively studied using the physical
simulator PSCAN [10, 11] which currently can verify
and optimize circuits comprising up to a few hundred Josephson
junctions (each described by Eq. ()). The parameters in the
schematic are in dimensionless PSCAN units (see Table\
in Appendix ).
Comparison of the JTL in Fig. to that in Fig.
shows that the ``real-life'' version uses one current source I1 for
biasing of both junctions and has ``parasitic'' inductances between
junctions and the ground. The corresponding layout for HYPRES' 1-kA
process [7] is shown in Fig. . The two
L-shaped figures in the picture are the junctions with shunting
resistors, the long horizontal metallic strip (marked ``PIN'',
``POUT'') is the signal inductance and the bar labeled ``I=2.81'' is
the biasing resistor.
Figure: Transient dynamics of a one-way JTL simulated
using PSCAN software package [10, 11]
This JTL is symmetric and transmits SFQ pulses in both directions
which can be an undesirable or even dangerous feature in some cases. A
one-way JTL (diode) with a buffer stage is shown in Fig. . When applied to the J0-J1 comparator, SFQ voltage pulse
induces a 
phase jump in junction J0 (or, in other words,
magnetic flux escapes through junction J0) and almost nothing from pin
``out'' appears on the pin ``in''. This is illustrated in
Fig. which shows the transient dynamics of one SFQ pulse
successfully going from ``in'' (J1) to ``out'' (J2) and one SFQ
pulse unsuccessfully attempting to get from ``out'' to ``in''.
Many other JTL variations are possible, but I will mention only one
more: a ``slow'' or ``delaying'' JTL which simply has an additional
shunting resistor (Fig. )
which effectively reduces the 
parameter of the JTL junctions
(when the additional ``delaying'' resistor R gets very small
unshunted junctions may be used in the layout). SFQ pulses delayed in
this manner become flatter and may require some sharpening by a
junction with 
.
JTLs form the universal ``glue'' of any RSFQ design, allowing the
output of any cell to be matched with the input of another and the
speed of propagation and other properties of an SFQ pulse to be
controlled. Delay introduced by JTLs is substantial ( 
per
junction) and a circuit built of standard blocks interconnected with
JTLs may have a surprisingly low maximum operating frequency unless it
has been carefully optimized for such delays. In some cases, when a
signal has to be transferred across a large distance (say, across a
chip) this delay makes JTLs absolutely impractical for most
digital applications. Fortunately, junctions can be matched with long
passive microstrip lines [12] and SFQ pulses can be
transferred with low loss and dispersion over distances of the order
of 
with speed approaching the speed of light.
