Until very recently, development of superconductive CAD tools was focused mostly on separate aspects of the design process and many stand-alone programs were created. These include Stony Brook inductance extraction programs ``L-Meter'' and ``lm2cir'', physical simulator PSCAN [10, 11] with a built-in functional description and verification language (SFQHDL, Single Flux Quantum Hardware Description Language), parameter optimization program COWBoy (Circuit Optimization WorkBench) [11] and many others. Integration of all these tools into Cadence not only speeded up the design process, allowing, for example, fast reoptimization of the circuit with parameters extracted from the layout, but also added new, extremely important functionality.
1. Layout-Versus-Schematic (LVS) Verification. Typically,
acceptable parameter variations in an RSFQ device are in the range of
(see Chapter 
). From a designer's point of
view, this translates into requirement to verify parameters of all
inductances, junctions and resistors in a design, since even a single
error in any one of them can render the entire device inoperational.
``L-Meter'' inductance extraction program, while providing quite
accurate (better than 
) values of inductances, cannot process
designs bigger than 
Josephson junctions. Cadence's
Layout-Versus-Schematic verification program, on the other hand, not
only allows to crudely (with accuracy of around 
) check
values of all major inductances in an arbitrarily large design, but
also critical currents of all junctions and values of all resistors
(with a few per cent accuracy). Simultaneously, it allows to eliminate
``macroscopic'' errors, checking for correct connectivity of the
building blocks and power supply lines.
2. Hierarchical Netlister for Physical Simulation. Even the
relatively narrow parameter margins of are only achievable
after extensive physical simulation and optimization of all major
blocks in the design, careful matching of all inputs/outputs, combined
with verifying the circuit for correct functionality and timing. For
circuit sizes of up to several hundred Josephson junctions this task
is successfully performed by hierarchical PSCAN/COWBoy (see discussion
in Chapter and Appendix ). In our view,
development of a hierarchical netlister for PSCAN not only enhanced
efficiency and accuracy the schematic design but also contributed to a
deeper understanding of the timing requirements in RSFQ design.
3. Logical Verification with Verilog. Circuits larger than several hundred Josephson junctions can be verified only on the logical level, for example, with a Verilog simulator. Adaptation of the Verilog (or any other logical simulator) for description of an RSFQ design is not a straightforward problem, since Verilog assumes voltage-state logic while RSFQ is essentially event-based and operates on voltage pulses.
4. Design Rule Checker. Also, the final design should be checked for compliance with many technological requirements (``design rules'', see, e.g., [7]) which is not a trivial task, especially for a large hierarchical design.
5. Automated Generation of Resistor and Inductance Layouts. Two SKILL scripts with graphic interfaces for automated generation of resistor and inductance layouts greatly improve the speed and the accuracy of layout design. Bias resistors can be generated for a given nominal value of bias voltage (or to have a given ohmic value), of different widths and, optionally, be composed of several parts. Inductances of given value in a chosen layer are generated to have a graphically entered shape which is also checked for compliance with design rules. Automatically generated resistors and inductances are ready for LVS extraction and netlisting.