Fig. 
shows a typical flow diagram of RSFQ design
process.
Figure: Flow chart of RSFQ design process.
Usually, the first step is a creation of a hierarchical (or flat)
schematic entry with functional description in hSFQHDL (see Appendix
) for simulation and optimization with PSCAN/COWBoy
software package. Currently, physical simulation is limited to several
hundred junctions. A substantially larger ( 
junctions)
circuit can be simulated only with a logical simulator, for example,
with Verilog.
After the circuit has been optimized and satisfactory parameter margins have been achieved, the next step is layout design. Two of the most time-consuming operations - creation (with correct parameters) of the bias resistors and quantizing inductances had been automated to a large extent in the framework of layoutPlus with the help of special SKILL programs. Then, the layout is checked for compliance with design rules (DRC) and verified against the schematic (LVS). Accurate extraction of inductances from the layout is an essential step and is done with the help of ``L-Meter''and ``lm2cir'' programs. Typically, a schematic with inductances, extracted from layout has narrower parameter margins and requires reoptimization with PSCAN/COWBoy. After a few iterations, we arrive at the schematic-layout pair which has satisfactory parameter margins and, at the same time, a very close correspondence between values of inductances (and all other parameters) in the layout and in the schematic.