[55] (Cadence, DFII, layoutPlus,
SKILL and Verilog are trademarks of Cadence Design Systems, Inc.), the
semiconductor industry standard computer-aided-design (CAD) tool, has
been calibrated for HYPRES' Nb-trilayer process [7] with
interfaces to Stony Brook in-house programs ``L-Meter'', ``lm2cir''
and PSCAN [10, 11]. As a result, a complete design
system was build, allowing creation and verification of complex
( 
and more Josephson junctions) RSFQ devices.
The principal features of this system include:
) simulation;
;
;
lines of code) Verilog library
of RSFQ cells.
The heart of the system is 
lines of original 
code with a number of auxiliary C, Perl and Tcl
programs. The total size (in Cadence format) of all schematic and
layout libraries created by Stony Brook RSFQ Laboratory in the
framework of this system is close to 1 Gb.
In our view, the created Cadence-based RSFQ design framework was of
crucial importance in improving the accuracy and efficiency of the
RSFQ design to the level when successful creation of large-scale ( 
Josephson junctions) projects like the ones described in
Chapters 
, and became
possible. Currently, all major Stony Brook RSFQ projects (for a
review, see [3]) are developed within the Cadence-based
framework.
Independently, a different Cadence-based design environment for SFQ circuits was developed at the University of Rochester [56]. This environment is integrated with a entirely different set of tools for circuit-level simulation, inductance extraction and others (see [56] for further references).