Hierarchical description of RSFQ circuits

  hSFQHDL is very useful for rapid construction of large RSFQ designs. For example, the number of 2-junction JTLs used in a single stage of the delay line varied from 18 to 22 in different versions of our autocorrelator. Without hSFQHDL, the designer would have had to rewrite the script of the entire design every time a JTL stage is introduced or removed from the schematic, which is not a simple task, considering the fact that a typical flat SFQHDL description of a 100 junction design averages 1,000 lines or so. With hSFQHDL, every building block (JTL, splitter, D-flip-flop, etc.) is described only once and then can be used any number of times in any combination with other blocks. To illustrate the basic features of hSFQHDL, let us consider a typical fragment of the circuit, containing a D-flip-flop with inputs connected to standard JTLs, see Fig..

 
Figure:  Example of a hierarchical design:\ (a) - top cell made of three JTLs and one D-flip-flop;\ (b) - schematics of a JTL;\ (c) - schematics of a D-flip-flop.

The hSFQHDL description of the D-flip-flop (see Fig.) is:

value
   In?   = >>in > (N(J0)+N(J1)),
   Clk?  = >>clk > (N(J2)+N(J3)),
   <rule  in0?(In? and S0?)
   inc(J1);
rule in1?(In? and S1?)
   inc(J0);
rule  clk0?(Clk? and S0?)
   inc(J3);
rule  clk1?(Clk? and S1?)
   inc(J2);

and the hSFQHDL description of a standard JTL (see Fig. ) is:

value 
   <>in > N(J1);   
rule  main? ( in? )
   [inc(J1),
   inc(J2)];

During the netlist of the top cell (Fig. ) these hSFQHDL descriptions are combined into one flat SFQHDL script:

value          {script for cell JTLin} 
   Z9 = N(J17) ,
   W1 = Z4 > N(J18);   
rule  W3 ( W1 )
   [inc(J18),
   inc(J17)];
value          {script for cell JTLout}   
   Z5 = N(J5),
   W2 = Z12 > N(J6);
rule  W4 ( W2)
   [inc(J6),
   inc(J5)];
value          {script for cell JTLclk} 
   Z7 = N(J11) ,
   W5 = Z2 > N(J12);   
rule  W7 ( W5 )
   [inc(J12),
   inc(J11)];
value          {script for cell D} 
   W10   = Z9 > (N(J26)+N(J24)),
   W11  = Z7 > (N(J25)+N(J27)),
   Z12 = N(J25),
   W12 = N(J24) eq N(J25),     
   W13 = N(J24) eq (N(J25)+1); 
rule  W15(W10 and W12)
   inc(J24);
rule  W16(W10 and W13)
   inc(J26);
rule  W17(W11 and W12)
   inc(J27);
rule  W18(W11 and W13)
   inc(J25);
end

Now it is easy to see how this works:

• first, all the element names are mapped from hierarchical to flat names, for example, junction J1 in cell JTLin is mapped into J18, and junction J1 in JTLout is mapped into J6,
• second, all value and rule names marked with ``?'' are given unique identifiers, for example, rule ``main?'' in JTLin becomes ``W3'' in the flat script,
• third, all values marked with ``<<'' and ``>>'' are mapped into flat names in accordance with the design connectivity.

All connected ports in the design form ``import-export'' pairs, with one port exporting the logical information from one cell and another port importing it into the other cell. For example, import value ``>>in'' of the D-flip-flop became ``Z9'', which is the same identifier as export value ``<<out'' of the JTLin received in the flat script. This is how the logical information is transferred from cell to cell. hSFQHDL allows a bi-directional exchange of logical information, for example, the ``in''port of the D-flip-flop could also be assigned export value ``<<in'', and the ``out'' port of the JTLin could be assigned import value ``>>out''. In a flat script the ``<<in->>out'' pair of these two cells would get a unique flat name, different from the name ``Z9'', received by the ``>>in-<<out'' pair.

Another important feature of hSFQHDL is the ability to reference the internal states of the cells on any hierarchy level. For example, a timing requirement, stating that clock pulse should arrive at the clock input of the D-flip-flop before the signal pulse can be introduced into the script of the top cell in the following simple form:

rule race? ( ... )
  JTLclk/in?,
  JTLin/in?;