Testing

Delay lines (with multipliers) of lengths 2, 4, 8 and 16 have been successfully tested at low frequency, using experimental setup ``Octopux'' [24]. Figure shows the correct operation of an 8-stage delay line for the test sequence when a train of ``1'''s (signal AIN in Fig. ) is loaded into the circular shift register and is read from the output BOUT with the delay of 18 clock cycles. It demonstrates the correct operation of all 8 XOR gates (outputs Q1-Q8) for all 4 possible combinations of inputs (``00'', ``10'', ``01'' and ``11''), as well as the correct operation of the circular shift register under a full load. The experimental power supply margin for this test sequence was . 16-stage delay line had a power supply margin for a fully loading test sequence analogous to the one shown in Fig. .

We have also successfully tested at low frequency a 16-stage delay line with 3 rows of T flip-flop counters attached to outputs Q9-Q16 (Fig. ). For a fully loading test sequence analogous to the one shown in Fig. , the power supply margin of this design was .

 
Figure:   Low-frequency testing of the 8-stage autocorrelator delay line. For inputs AIN and CLKIN each rectangular pulse corresponds to an SFQ pulse, for outputs BOUT and Q1-Q8 every rising and falling edge corresponds to an SFQ pulse.

 
Figure:   Fully operational 16-channel digital delay line with XOR multipliers integrated with an array of T flip-flop counters. Total number of Josephson junctions: 821, total number of logic gates: 72. Chip size: . Nominal bias voltage: 2.6 mV.

The array of 8 low-power T flip-flops has been successfully tested at both low and high frequencies. The high frequency experiment was carried out by applying dc voltage to an overdamped junction and feeding the resulting train of SFQ pulses into the array of 8 low-power T flip-flops after prescaling it in the array of 4 conventional T flip-flops. The observed ratio of the applied voltage to the frequency of the pulses at the array output has been found to be in agreement with the fundamental Josephson voltage-to-frequency relation. No significant degradation of the power supply margin has been observed at frequencies of up to at the input of the low-power array.