With 10 T flip-flop binary counters per autocorrelator stage,
prescalers are the largest part of the design, responsible for some
2/3 of the total junction count. If designed for the same nominal
bias voltage as the delay line, they would have also been responsible
for roughly 2/3 of the entire power dissipation. On the other hand,
good parameter margins (above 
) and low frequency of
operation make T flip-flop counter a perfect starting point for any
attempt to further reduce power dissipated by RSFQ circuits. In fact,
simulations have clearly demonstrated that in this particular case
bias voltage of only 
can be used, which is significantly
lower than the minimal voltage of 
estimated in Chapter
for the general case. The final version of the
low-power T flip-flop counter had simulated parameter margins in
excess of 
on power supply for frequencies up to 
. Parameters of the cell are shown in Fig.. T flip-flop
is a two-state cell which operates as an RS flip-flop (trigger)
[1] with joined set and reset inputs so that input
every pulse triggers its switching to the opposite state and thus
divides the frequency of the input pulses by 2. Junction J0 is
optional and operates as a one-stage JTL. Layout of a single cell
(Fig. ) done in the standard 
- 
- 
HYPRES' technology [7] has dimensions
of 
with estimated power dissipation of 
.
Figure: Layout of the T flip-flop cell. Nominal bias
voltage: 0.1 mV. Dimensions: .
