Design of the autocorrelator delay line follows closely the one
proposed in [48]. It is based on the circular shift
register first described in [53] with XOR gates
integrated into every stage. A characteristic feature of this delay line
is that XOR in n-th stage operates on signals delayed by 2n
sampling intervals thus making it a natural choice for designs with
double oversampling, see Eq. (
). This unique coincidence was not
used in [48], where sampling at Nyquist frequency
with sample replication was proposed.
Using hierarchical approach (see Appendix and
Ref. [45]) and the automated design centering Circuit
Optimization Work Bench (COWBoy) [11] program build on top
of PSCAN [10] we were able to optimize the parameters of a
2-stage delay line (stages 0, 1 and 2) as a whole. Further
improvement of the design quality was achieved by performing
post-layout reoptimization of a 2-stage delay line with parasitic
inductances extracted with Stony Brook in-house programs L-Meter and
lm2cir and by calculating the margins of a 4-stage delay line. (RSFQ
design process is described in greater detail in Appendix
.) The final design has simulated parameter margins of
more than 
for the power supply voltage. Each stage of the
delay line (Fig. ) comprises 22 Josephson junctions and
its layout for the standard 
- 
- 
HYPRES' technology [7] occupies area of
, with estimated power dissipation of 
. Most of this power is dissipated in the biasing resistors and is
directly proportional to the bias voltage. In Chapter
we argued that by lowering the bias voltage for the delay line from
its traditional value of 
(which was accepted here) to around
this power dissipation can be reduced to about 
per stage without any significant degradation of the parameter
margins.
Figure: Layout of a single stage of the delay line.
Nominal bias voltage: 2.6 mV. Dimensions: .