The 1-bit double-oversampling autocorrelator computes the following digital function:
where 
is the 1-bit
quantized input signal sampled at double Nyquist frequency 
, n is
the stage (or ``lag'') number and N is the number of accumulated samples.
In our design the sign of an input signal +1 or -1 is coded as binary ``0'' and ``1'', respectively. Let a(i) be representation of sign(x) in this coding, then
Thus the 1-bit multiplication can be performed using a simple XOR
function. Summation in (
) can be done with binary counters
of length 
. For a sampling rate of more than 10 GHz and
typical integration periods exceeding 10 milliseconds
[30], M is never less than 
. From
statistical considerations [29], (M/2)-3 least
significant bits can be safely discarded. For our design it means that
the first 10 bits in each stage can be counted by simple T flip-flops
and at the sampling rate of 16 GHz the output rate of the last
T flip-flop will be less than 16 Mbps. This low frequency signal can
be readily transferred to and further processed by standard
room-temperature electronics [17].
Possible hardware implementation of a 16-stage autocorrelator is shown
in Fig. . Autocorrelator forms a linear array with two main
parts: digital delay line with multipliers and an array of T flip-flop
prescalers.
Figure: Block diagram of a 16-stage autocorrelator.
