We experimentally verified the correct operation of all major blocks
of the correlator at low frequency for different levels of
integration using experimental setup ``Octopus'' [52]. The highest levels of circuit integration achieved so far
are a 3-stage delay line and a 
accumulator.
A complete test sequence for the 3-stage delay line is too long - the
minimum length of an exhaustive test sequence is over 31,000 clock
periods. To verify the operation of the digital delay line we have
selected a representative test sequence of length 18 which covers
most of the operations performed by the array. Results of
low-frequency testing for this sequence are shown in
Fig. 
. Input currents 
and
I(bin) are in ``pulse-representation'', so that one full rectangle
pulse corresponds to one SFQ pulse injected into the array. Output
voltages U(q1), U(q2), U(q3), U(bout), U(aout) and
U(naout) are in the ``edge-representation'', so that each raising or
falling edge corresponds to an SFQ pulse read from the delay
line. Table illustrates the internal states (after the clock)
of the D-flip-flops. Power supply margin for this test sequence was
around the nominal value of 
. This margin is
significantly smaller than that of a single stage on the same chip
( 
). This margin degradation could be ascribed to
fluctuations in fabrication process.
The total number of states of a accumulator array is
. For a representative test sequence of length
the
margin on power supply was 
.
Figure: Low-frequency testing of the 3-stages array of the delay line.
Table: STATES OF THE D-FLIP-FLOPS IN THE 3-STAGE DELAY LINE (FIG.) FOR THE TEST SEQUENCE SHOWN IN FIG.