Accumulators

Integration and low-frequency read-out of the sum (functions 4 and 5) are performed in the accumulator block implemented as a two-dimensional matrix of cells (see Fig. ), based on the B-flip-flop template [14].

 
Figure:   Single stage of the accumulator array.

Each part of the cell implements a separate function:

• Integration is carried out by binary counters made from the T part of the B-flip-flop (vertical direction of signal propagation in Fig. ).
• Read-out is performed by counter-clock-flow shift register formed by the RS part of the cell (horizontal direction).

Our main concern in optimizing this cell was to minimize hardware consumption, while timing constrains were not as restrictive as in the case of the delay line. Simultaneous cell optimization approach proved to be very useful in this case as well since it allowed us to minimize the Josephson junction count in the interconnecting JTLs. Simulations were performed on up to arrays of flip-flops.

The final design of the accumulator cell has simulated margins of on power supply. The cell consists of 18 Josephson junctions, with estimated power dissipation of and occupies area . Physical layout of the cell is shown in Fig. .

 
Figure:   Layout of the cell. Dimensions are .