Block diagram

The 1-bit double-oversampling correlator computes the following digital function:

where is the 1-bit quantized input signal sampled at double Nyquist frequency , n is the stage (or ``lag'') number and N is the number of accumulated samples.

In our design the sign of an input signal +1 or -1 is coded as binary ``0'' and ``1'', respectively. Let a(i) and b(i) be representations of sign(x) and sign(y) in this coding, then

 

Thus the 1-bit multiplication can be performed using a simple XOR function. Summation in () can be done with binary counters.

Possible hardware implementation of a 16-stage correlator is shown in Fig. . In this design Q(n) is represented as a 24-bit number with 8 LSB's discarded (this part of the output signal is close to white noise) and 16 MSB's B0-B15 read out into the room-temperature interface.

 
Figure:   Block diagram of a 16-stage autocorrelator.

Each stage of the correlator performs the following functions:

1. asynchronous propagation of dual-rail coded undelayed signal,
2. delay (by two clock periods) and shift of the delayed signal,
3. multiplication of undelayed and delayed signals,
4. summation of the sequential products,
5. parallel read-out of the sum.

The correlator as a whole operates in two time-sequential modes:

1. High-frequency accumulation.
2. Low-frequency read-out.

Functions 1-4 constitute mode I, function 5 is used in mode II.

Throughout the design we employ two types of logical data representation: the ``traditional'' RSFQ representation [1] and dual-rail SFQ representation, where an SFQ pulse in one Josephson transmission line (JTL) represents logical ``1'', while an SFQ pulse in the other represents logical ``0'' (independently such representation was suggested by the Berkeley group [50]). The coding of physical data and its representations are summarized in Table .

 
Table:  Data representations used in the correlator design.