XOR gate which is a key component and the main object of study in this
experiment was first proposed in [1]. It was studied
experimentally a few years later [44] at low
frequency. The experimental bias window of 
[44] is the widest ever measured for any RSFQ gate
performing a logic function. Equivalent circuit of the XOR cell is
shown in Fig. 
.
Figure: Equivalent circuit of the XOR cell
All circuit parameters in Fig. are in PSCAN units (see
Appendix ). Operation of the circuit is as follows:
input SFQ pulse ``A'' enters through junction JXA1 and inserts a flux
quantum into the loop JXA1-JXA2-LXA-JXO2-JXO1 (similarly for input
``B''). When there is no inputs and both ``A'' and ``B'' loops are
empty, the incoming clock pulse ``CLOCK'' induces a 
phase leap
in junction JXC and there is no output pulse across junction JXO1
( 
). When there is only one input pulse, the current
through the corresponding quantizing inductance (LXA or LXB) biases
the two-junction comparator JXC-JXO1 so that the next ``CLOCK'' pulse
flips junction JXO1 rather than JXC and we obtain an SFQ pulse on the
output ``XOR'' ( 
). This SFQ voltage pulse
clears the loop with a flux quantum but is also applied to an empty
loop, so junctions JXA2 and JXB2 are necessary in this case to work as
buffers (when in the empty loop), preventing JXA1 and JXB1 from making
a jump in phase and thus injecting parasitic backward-moving
SFQ pulses into the outside circuit. Operation 
is
performed by junction JXO2 when both quantizing loops have an SFQ
inside. In this case the total current through JXO2 exceeds its
critical value and the junction flips, clearing both loops. This
process starts asynchronously, as soon as both ``A'' and ``B'' are in
and has to finish before the arrival of the clock signal. Ideally,
when the clock pulse arrives, it finds the gate in the same state as
in the case of zero inputs.
The physical layout of the XOR gate is shown in Fig. . The
gate was a part of a rather densely packed layout of the correlator
delay line, so the positions and orientations of the XOR junctions
were dictated mostly by the positions and orientations of the
neighboring junctions, not shown in the picture. The central part of
the layout are the two quantizing inductances connecting JXO2 with
JXA2 and JXB2. The large inductances of the bias line are not shown.
Note that for the nominal dc bias value of 
the bias resistors
are smaller than the shunts.
Figure: Layout of the XOR cell. Nominal bias 0.1 mV.
Approximate size is 
.
Parameters shown in Fig. correspond to the values extracted
from the physical layout (Fig. ) of the circuit used in the
experiment. The extraction was done with Stony Brook in-house programs
``L-Meter'' and ``lm2cir''. As a part of an autocorrelator stage, the
circuit was extensively simulated and optimized with PSCAN/COWBoy
software package [10, 11]. Simulated noise-free bias
margin for a separately biased 
XOR gate inside the
autocorrelator delay line was 
for a full input
sequence at 
clock. In simulation, we could also observe the
shrinking of the lower margin for smaller bias voltages so that at
bias the margin was close to 
(with the same
test sequence and the same clock speed).