Block diagram of the experiment is shown in Fig. . Its main feature is the 4+1-stage circular shift register with input signal ``ain'', formed by 10 D flip-flops clocked by the ``clkin'' signal. Every clock shifts the contents of each D flip-flop into the next stage so that the contents of (``0'' or ``1'') move into , contents of into and so on until, finally, after 10 clock periods, the signal gets out and is read from output ``BOUT''. The upper branch (cells ) is a ``co-flow'' shift register in which clock and data are moving in the same direction (we have to make sure that clock moves faster than data) while the lower branch (cells ) is a ``counter-flow'' shift register with clock and data moving in the opposite directions (here timing requirements are more relaxed, since data and clock pulses do not race). Clock propagation path and D flip-flops were dc biased separately with nominal bias for both. Additionally, we had 4 XOR gates build into every stage of the shift register each having a separate bias line. XORs 4, 3, 2 and 1 had nominal bias voltages of and , respectively. Parameters of each stage were optimized for the following sequence of events to take place within every clock period: the clock pulse arriving from the previous stage (say, stage 4) resets the XOR gate (XOR3 in our example) and the result is read into the output SFQ-DC converter (``Q3''); almost immediately (in a few picoseconds) after that, the contents of the upper D flip-flop in the same stage ( ) is fed to the upper input of the XOR and contents of the lower D flip-flop from the next stage ( ) arrive to the lower input of the XOR. This choice of timing ensures that XOR has almost the entire clock period (until the next clock pulse) to reach its final state based on the contents of both inputs. The slowest and most untrivial XOR operation is . The rest of the hardware in Fig. is used for low- and high-frequency testing of the circuit. Low-frequency testing is done with standard DC-SFQ converters for input of ``CLKIN'' and ``AIN'' SFQ pulses. This allows to check operation of the circuit at low frequency for an arbitrary sequence of input signals. Notice that even at this ``low-frequency'' testing the time interval between the clock and data arriving at each XOR gate (and at each of the upper D flip-flops) is still very short (a few picoseconds).
High-frequency testing is based on the on-chip clock generator ``clkgen'', which is basically an overdamped Josephson junction controlled by dc current source ``CLK'' (we could also measure dc voltage across this junction and hence the frequency of the clock), and a two-junction comparator controlled by current ``SIG''. The on-chip clock generator allows flexible variation of the frequency in a very wide range, approximately . Array of 19+1=20 T flip-flop cells (standard SFQ-DC converter contains one T flip-flop) divides the frequency of the clock signals by a factor of and allows to monitor them digitally at very low frequency (in the kHz range). The comparator allows to apply two different high-speed input sequences to the circuit: all ``1'' or all ``0'', depending on the value of the current ``SIG''. When current ``SIG'' is inside the ``gray zone'' of the comparator we get a random sequence of ``1'''s and ``0'''s with one of them starting to dominate when we move away from the center of the ``gray zone''.
Figure: Block Diagram of the Bit Error Rate Experiment