The theoretical analysis in the previous chapter gives convincing
evidence that a dramatic reduction in dc power dissipation can be
achieved with relatively simple means. First tests in 1996 (see
Chapter 
) of low-power ( 
30 nanowatt) T flip-flop
gates at 7 GHz preliminary confirmed this conclusion. At that
stage it was not clear, however, how reduction of bias voltage would
affect margins and high-speed behavior of a clocked gate. At the same
time, a detailed study of the bias margins requires an error rate
measurement. So far, several rare-error experiments have been reported
[42, 43] aimed mostly at achieving record
numbers ( 
in [43], 
in
[42]). None of these experiments was designed to
demonstrate the detailed error rate dependence on dc bias or their
variation with frequency. Moreover, only the simplest gates such as a
JTL buffer stage were the object of study. Authors of
[42] admitted that ``...one might expect the most
prevalent errors to arise during the interaction of flux quanta, such
as in a clocked gate, but there is no experimental information about
this situation...'', so study of a timed logical cell (such as XOR) is
of great interest.
Typically, error rate measurements use XOR gates to compare two
streams of binary data and digitally flag the rare cases when these
streams differ. We have proposed a different approach to error rate
measurement: use the same stream of binary data to feed several XOR
gates and study rare errors in XOR gates themselves by
independently changing their bias, while simultaneously using other
XORs as means to verify that error occurred in XOR rather than in the
incident data stream. For us, this is a particularly suitable approach
since we could use (with some modifications) the already existing
layout of the autocorrelator delay line described in Chapter
.