Power dissipation in a typical RSFQ circuit comes from two main
sources. First, power is dissipated in the shunt resistor when the
junction is in the resistive state during generation of an SFQ
pulse. Total energy 
dissipated during this process of
a 
phase jump is of the order of
Here 
is the critical current of the junction and 
is the
magnetic flux quantum. As discussed in the Introduction, cannot
be made smaller than a certain limit ( 
) set by
thermal fluctuations [1] and, therefore, nothing can
be done to further minimize (if we do not go after the
reversible computation [41] which is slow and hardware
consuming). When a part of an RSFQ design operating at clock frequency
f, Josephson junction lets through of the order of f SFQs per
second and dissipates power
The main source of power
dissipation, however, is the second contribution: DC power dissipated
in the biasing resistor. Biasing of the junctions is essential for
RSFQ devices. Consider for example a stage of JTL in Fig. 
.
Figure: JTL with a biasing line
Instead of the short-hand symbolic notation for the biasing current
sources which was used throughout the Introduction and is convenient
for circuit simulation, schematic in Fig. is closer to the
physical layout with biasing resistors (see Fig. )
connected to a common voltage source V. Bias current 
should
be smaller than the critical current of the junction but close
enough to it so that junction is capable of making a jump in
phase under the influence of an incoming SFQ pulse. Correct operation
of the circuit limits variation of the bias voltage V (and,
hence, of the ) to a certain range
roughly limited from above by the 
and from below by the minimum
bias when a junction still can make a phase jump under the
influence of an SFQ pulse. This variation can be found in simulation
and measured in experiment and usually is presented in the form of a
relative bias margin 
:
Empirical rule of thumb in RSFQ is that it is hard to make a
complex circuit with more than a 
bias margin, so we
can crudely accept that 
.
Although other biasing schemes may be possible, the one depicted
in Fig. seems to be the most practical, especially
for large designs. Power dissipated in biasing resistor is
simply
Traditionally, all RSFQ layouts were done for the value of bias
voltage close to 
which is roughly the gap voltage of the
Nb. The reasons for this choice were that, first, sufficiently large
bias voltage ensures that all the effects of junction interaction with
the bias line (which are the main topic of this chapter) are minimal
and, second, this voltage could, in principle, be stabilized by the
current step at 
of an unshunted
Josephson junction. This choice of bias voltage, however, results in a
very large dissipation of DC power 
as compared to the
fundamental limit 
:
The last numerical estimate was done for and 
.
Eq. () shows that, although it is impossible to push the
bias voltage below the fundamental limit of 
, a considerable
(of the order of 10) gain in power dissipation can be achieved simply
by lowering the bias voltage V closer to that limit. The dangers of
this straightforward approach include possible shrinking of the bias
margins and interaction of the junctions through the bias line so that
a detailed study of the processes in an RSFQ biasing line is
necessary.
