List of Figures

• I-V curve of an overdamped Josephson junction
• Single flux quantum entering a J1-L1-J2 stage of a Josephson transmission line (JTL) through junction J1.
• Two-junction comparator controlled by a quantizing inductance
• Symmetric JTL
• Layout example
• One-way JTL
• Transient dynamics of a one-way JTL simulated using PSCAN software package [10, 11]
• Splitter
• Confluence buffer (merger)
• Confluence buffer (merger)
• Characteristic curve for two-level quantization.
• Analog lag correlator architecture. Lag spacing is . ``x'' and ``y'' are signals to be correlated. After [34].
• JTL with a biasing line
• A simple model circuit for estimation of transients in an RSFQ biasing line.
• Currents (in units of ) through junctions n=1..10
• Block Diagram of the Bit Error Rate Experiment
• Equivalent circuit of the XOR cell
• Layout of the XOR cell. Nominal bias 0.1 mV. Approximate size is .
• Low frequency testing of the 4 stage delay line
• I-V curve of the clock generating junction
• 4 GHz Josephson oscillations observed as 1 kHz digital output. Upper window shows the real-time signal, lower window shows its Fourier transform. The picture was generated with experimental setup ``Octopux'' [24].
• I-V curve of the ``comparator + autocorrelator delay line'' system. Taken at clock speed. The voltage averaging time was 5 ms.
• Bit error rate versus normalized bias voltage for operation. Solid vertical lines show dc margins for , dashed vertical lines show dc margins for a fully testing sequence.
• Relative total width of the bias window as a function of clock speed at error rate.
• Minimum error rate versus clock speed.
• Block diagram of a 16-stage autocorrelator.
• Three stages of the digital delay line.
• Single stage of the accumulator array.
• Layout of the cell. Dimensions are .
• Low-frequency testing of the 3-stages array of the delay line.
• Block diagram of a 16-stage autocorrelator.
• Layout of a single stage of the delay line. Nominal bias voltage: 2.6 mV. Dimensions: .
• T flip-flop.
• Layout of the T flip-flop cell. Nominal bias voltage: 0.1 mV. Dimensions: .
• Low-frequency testing of the 8-stage autocorrelator delay line. For inputs AIN and CLKIN each rectangular pulse corresponds to an SFQ pulse, for outputs BOUT and Q1-Q8 every rising and falling edge corresponds to an SFQ pulse.
• Fully operational 16-channel digital delay line with XOR multipliers integrated with an array of T flip-flop counters. Total number of Josephson junctions: 821, total number of logic gates: 72. Chip size: . Nominal bias voltage: 2.6 mV.
• Block diagram of the high-speed experiment.
• Layout of the 16-channel autocorrelator. Total number of Josephson junctions: 1636.
• Output of the autocorrelator fed by a harmonic signal. Circles show experimental points, dashed line is theory for . In this experiment we had and .
• Output of the autocorrelator fed by a harmonic signal. Circles show experimental points, dashed line is theory for . In this experiment we had and .
• Output of the autocorrelator fed by a harmonic signal. Circles show experimental points, dashed line is theory for . In this experiment we had and .
• Output of the autocorrelator fed by a harmonic signal. Circles show experimental points, dashed line is theory for . In this experiment we had and .
• Example of a hierarchical design:\ (a) - top cell made of three JTLs and one D-flip-flop;\ (b) - schematics of a JTL;\ (c) - schematics of a D-flip-flop.
• Flow chart of RSFQ design process.