This cell has many different names: RS (reset-set) flip-flop
(trigger), D flip-flop, etc. and is at the basis of every RSFQ design
(Fig. 
). It has two states ``1'' and ``0'', i.e. with and
without an SFQ pulse inside the J1-L1-J2 loop. Inductance L1 is
quantizing and an SFQ pulse entering the loop through the junction J1
(``set'' signal) waits until it is released by the ``reset''
signal. Junction J0 is optional and acts as a buffer in case two
``set'' signals arrive before the ``reset'' signal.
Figure: Confluence buffer (merger)
Without junction J0, D flip-flop is just a direct combination of
a JTL (Fig. ) and a controlled two-junction comparator
(Fig. ). D flip-flop with two inputs (a truncated version
of a more general B flip-flop [14]) can be obtained by
making the output inductance of the confluence buffer (inductance L7
in Fig. ) quantizing and controlling a two-junction
comparator .
RSFQ is a growing collection of ideas rather than a fixed set of rules
and many other RSFQ cells have been developed (for the latest results
see materials of 1994 and 1996 Applied Superconductivity Conferences,
[15, 16]) and further possibilities are practically
endless. Two other cells - XOR and T flip-flop are very important for
the autocorrelator project and will be discussed separately in
Chapters and .