Merging of pulses cannot be done by a JTL with two inputs: an SFQ
pulse on one input will appear not only on the output but on another
input as well and propagate into the circuit preceding that input. Two
buffer stages solve the problem, isolating one input from another, as
shown in Fig. 
.
Figure: Confluence buffer (merger)
An SFQ pulse from the input ``in1'' enters through J1 and leaves
through J5, buffer junction J4 also makes a 
phase jump thus
preventing J2 from rotating and injecting a parasitic
backward-moving SFQ pulse into the pin ``in2''. In contrast to a JTL
or splitter which are very fast gates, capable of lossless processing
of SFQ pulses in rapid succession (ultimately, at very fast speeds,
these gates go into analog mode and can be characterized by an I-V
curve), a confluence buffer is a much slower gate, having a ``busy''
state while a buffer junction (J3 or J4) is making a jump
in phase. The arrival of another SFQ pulse to the same or different
input during this ``busy'' period is undesirable and may cause errors.
For example, the simultaneous arrival of two SFQ pulses - one on the
input ``in1'' and another on ``in2'' may result in only one outgoing
SFQ pulse [13]. Dual-rail data representation (see
Chapter for a detailed discussion) requires a
confluence buffer for reconstruction of the clock signal, while in
standard RSFQ (clock + data) logic clock signal needs only JTLs and
splitters for propagation which could result in faster circuit
operation.