D Flip-Flop with Two Readouts
Schematics
All parameters are in PSCAN dimensionless units.
This particular flip-flop has been optimized primarily for the lowest possible static I/O currents and matching I/O impedance, and secondary for the highest XI and XJ margins.
Mealey Machine
How It Works
This circuit is a D flip-flop J7-LM-... with replicated readout comparators J3/J4 and J1/J2. The D2 is a core of any networking switching circuit because it allows to destructively dispatch its contents D to any of the two outputs O1 or O2 using the right readout signal C1 or C2.Files, necessary to simulate the circuit.
Transient Waveforms
| Transition | Delay | Aplha |
|---|---|---|
| C1/O1 | 12.4 | 15.3 |
Layout
