| SUNY RSFQ Cell Library |
All parameters are in PSCAN dimensionless units .
This element produces an output SFQ pulse for each incoming pulse from either input.
Behaviour of the circuit when input pulse arrives at IN2 is symmetric. If two pulses arrive at both inputs close in time at least one of them always propagates to the output. If only one output pulse is produced, J1 (or J2) does not switch.
One half of the merger can be used as a "diode". It allows pulses to propagate from input to output while throwing away the pulses propagating backwards.
The delay of this merger is about 10 time units.
Merger can be used as non-latching or gate for the encoding of boolean values such that any number of pulses between two clock pulses correspond to logical 1 while no pulses correspond to logical 0. Any logic function can be implemented using only mergers and inverters (or and not is a complete set of boolean functions) if we use a special version of inverter which throws away extra data pulses arriving between two clock pulses.
View online the files necessary to simulate the circuit with Julia or download the whole compressed directory.
This cell was optimized for interconnectivity to be a part of cell library.
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Paul BUNYK
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