SUNY RSFQ Cell Library

RSFQ Inverter

Schematics

All parameters are in PSCAN dimensionless units .

This is a simple inverting latch. If data pulse arrives then the next clock pulse reads out '0' (no output pulse is produced), otherwise it reads out '1' (output pulse is produced). If more than one data pulses arrive between two clock pulses all except the first one are ignored.

Mealey Machine

FSM

How It Works

When data pulse arrives at input ri it propagates through junctions j1, j2 and switches junction j4. Inductance l4 is large enough and SFQ is stored in the loop j4-l41-l4-j5-l5. Subsequent data pulses can not enter the loop through j4 and switch junction j3 instead.

When clock pulse arrives at input tri it propagates through jt0 and chooses which junction (j5 or j6) to switch. If an SFQ is stored in the loop, j5 switches, otherwise j6 switches and output pulse is produced and exit through j6, j7.

Any logic function can be implemented using only mergers and inverters (or and not is a complete set of boolean functions).

View online the files necessary to simulate the circuit with Julia or download the whole compressed directory.

This cell was optimized for interconnectivity to be a part of cell library.

Transient Waveforms

Waveforms

Layout

Layout Photo

References

A. Yu. Kidiyarova-Shevchenko, A. F. Kirichenko, S. V. Polonsky, and P. N. Shevchenko, "New Elements of RSFQ logic/memory family", Ext. Abstr. of 3'd ISEC91, (1991), p. 200

Paul BUNYK

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