This is essentially not an elementary circuit, but rather a combination of two  D Flip-flops  (one formed by Josephson junctions J₁-J₄ and quantizing inductance L₁, and another by J₅-J₈ and L₂) and the asynchronous  merger  (J₉-J₁₁). The new feature of this combination is its synchronism: a single clock pulse CLK is split to two simultaneous clock pulses which read out information from the flip-flops in parallel, so that the corresponding output SFQ pulses (if any) arrive to the merger virtually simultaneously. This feature may increase parameter margins, since the merger may be optimized for the fixed (zero) time delay between input pulses, while the asynchronous merger should operate at arbitrary delay.
 
 

   The following waveform picture, borrowed from Ref. 2, has been apparently simulated for a critical current density of 0.5 kA/cm², and hence each picosecond on its horizontal scale corresponds to approximately 0.7 PSCAN units. The assumed I/O environment is unknown, but was probably presented by short pieces of the standard Josephson transmission line.

      1. Since the circuit is essentially a combination of two D Flip-flops  and a merger, its characteristics may be restored from those of the components. Nevertheless, this restoration is only approximate, since the whole circuit has been re-optimized to utilize the readout pulse synchronism (which the regular merger cannot hope for) for margin improvement. This seems to work: according to Ref. 1, the theoretical overall margins of this circuit are at least +/-30%.

        2. According to report [2], the only experimental circuit which has ever been tested operated properly with total dc bias margins of at least  +/-11%, but it is not clear how much of the margin budget has been consumed by random parameter variations.

      This circuit has been suggested (and its schematics optimized) by V. Semenov [1]. In contrast to other circuits described in this library, the layout, fabrication, and testing of this circuit have been carried out by the Tektronix group [3] which went out of the RSFQ business soon after that. This is why no good layout picture or photo is available.

O. A. Mukhanov, V. K. Semenov, and K. K. Likharev, "Ultimate performance of the RSFQ Logic Circuits," IEEE Trans. Magn., vol. MAG-23, No. 2, pp. 759-762, Mar. 1987.    S.V. Polonsky et al. "New RSFQ Circuits", IEEE Trans. on Applied Supercond., vol. 3, pp. 2566-2577, March 1993.     V.K. Kwong and V. Nandakumar, "Experimental evaluation of some RSFQ basic cells", IEEE Trans. on Applied Supercond., vol. 3, pp. 2666-2670, March 1993.