B Flip-flop is a multi-branch RSFQ cell which may serve up to 4 inputs (S_1,2 and R_1,2) and provide up to six outputs. (Besides the four Q output terminals shown above, output pulses may be picked from both sides of the quantizing inductance L₁).
    The circuit has a single quantizing loop (and hence just two stationary states). The loop is formed by inductance L₁ closed via the ground and two 4-JJ low-inductance loops (J₁, J₃, J₇, J₉  and J₄, J₆, J₁₀, J₁₂ ). The loops themselves are not quantizing, and hence switching of one junction (say, switching of J₁ by input pulse S₁) is rapidly followed by the switching of a complementary junction in the same loop, in this particular case J₉. Besides this feature, the operation of the B Flip-flop is similar to that of the  basic RSFQ Flip-flop.
    Due to the high symmetry of the device, it may serve as a template for several useful cells - see "Comments" below.

   In this simulation, the I/O environment was presented by short pieces of the standard   Josephson transmission line. The time scale assumes HYPRES' 1-kA/cm² technology for which 1 ps is close to 1 PSCAN unit.

    The plot shows in particular that the delay between an input pulse switching the flip-flop (say S₁) and the corresponding output pulse (Q₁ bar) is very short, close to 3 PSCAN units. This is typical for switching of a single junction, in this particular case J₁. However, the minimum distances between set/reset pules are much longer: simulations [1] have shown, e.g.,  that if tau₁ = tau₂, circuit margins decrease rapidly if each of the delays is reduced below ~20 PSCAN units. This is natural, since each flip flip switching involves sequential switching of two Josephson junctions (see "How It Works" section above) which should then settle well before they handle the next signal.

Comments

    A frequent statement is that B Flip-flop is a concept rather than a cell. In fact, to my knowledge, its full version has never been used in any practical RSFQ circuit. However, straightforward truncations of the basic circuit may give rather useful cells. For example:

        (a) the replacement of one of the quantizing rings (say, J₁, J₃, J₇, J₉) with a single-junction input gives the  D2 Flip-flop;
        (b) a similar truncation, complemented with a merger of a pair of S-R inputs (say, S₁ and R₁) leads to the  T1 cell;
        (c) a similar merger of both S-R input pairs gives a toggle flip-flop which may be convenient as an up-down counter [1] and for MUX/DEMUX operations [2].

    Moreover, complementing B Flip-flop with simple (1-2 junction) SFQ pulse delay stages allows to implement [1]:

        (a) a relatively slow but apparently robust NDRO cell,
        (b) a version of D Flip-flop with complementary outputs, alternative to  the version described in this library,

        1. S. Polonsky, V. Semenov, and A. Kirichenko, IEEE Trans. on Appl. Supercond., vol. 4, pp. 9-18, March 1994.
        2. A. Kirichenko, "High-speed asynchronous data multiplexing/demultiplexing", to be published in IEEE Trans. on Appl. Supercond., vol. 9, June 1999.