The circuit is essentially a combination of two D Flip-flops (one formed by  Josephson junctions J₁-J₄  and quantizing inductance L₁ and another formed by J₅-J₈  and L₂) and a nested, asynchronous system of 3 Josephson junctions J₉, J₁₀, and J₁₁). Clock signal CLK reads out the contents of each flip-flop into a non-quantizing loop (e.g., one formed by J₂, L₂, J₉, and J₁₁).
    If only one flip-flop was in state "1", it gives a flux quantum into the non-quantizing loop; then the series junction (e.g, J₉) is switched, and flux is falls out of the loop without giving any output signal.
    However, if both flip-flops were in state "1", they give fluxes into both non-quantizing loops simultaneously. In this case the induced currents in J₁₁ add up, and this junctions is switched before any of J₉, J₁₀ have enough time to do. Switching of J₁₁ procuces the output pulse OUT across this junction and also quenches switching of J₉, J₁₀.

  Unfortunately, these waveforms (borrowed from Ref. 1) are for unknown parameter values (see comments below). The I/O environment, as  usual, was presented by short pieces of the standard  Josephson transmission line. Time is in PSCAN units. A, B and C, D were two input pairs preliminary  merged to IN1 and IN2, respectively.

    1. To my knowledge, this circuit (first suggested in Ref. 1) has been never implemented experimentally, because ways were always found to circumvent AND function. Hence, no layout pictures.

    2. According to Ref. 1, its "critical parameter margin can be larger than +/-30%", but the optimized parameter levels are probably lost by now. Nevertheless, the circuit may be rather vulnerable to thermal fluctuations. It may be advisable to analyze it carefully before practical use.

    O.A. Mukhanov, S.V. Polonsky, and V.K. Semenov, "New Elements of The RSFQ Logic Family", IEEE Trans. on Magn., vol. 27, pp. 2435-2438, March 1991.