SUNY RSFQ Cell Library

D flip-flop

Schematic

Unless otherwise stated, all parameters here and below
are in PSCAN units (for 3.5 um).

Moore diagram

How it works

This basic latch is also known as RS (reset-set) flip-flop. It is build around a DC SQUID J1-L1-J2 which has two stable states: "1" and "0", i.e. with and without a magnetic flux quantum inside. In state "0", an SFQ voltage pulse applied to the input "in" enters the SQUID through junction J1 and is stored inside. In state "1" the dc current in the quantizing loop flows clockwise and as a result the junction J1 is biased very far from its critical current value. If another SFQ pulse applied to the input "in", it flips the junction J0 and the latch remains in state "1". If, instead, we apply an SFQ pulse to the "clk" input when the latch is in state "1", the junction J2 would flip, releasing the stored flux quantum and thus clearing the quantizing loop. In state "0" junction J3 is closer than J2 to its threshold value and an SFQ pulse "clk" flips J3, so that the latch remains in state "0". For a clocked operation in a bigger design, when all inputs arrive from previous stages (as in a shift register) junction J0 is not necessary.

The device was simulated and optimized with a phase sources and a matching JTLs at both inputs and a JTL and a resistive load at the output:

Here's are all the files (you can also view them online ) necessary to simulate the circuit with PSCAN. The I/O JTLs used for optimization of this version of D flip-flop are standard.

Waveforms

The waveforms show voltages across all 4 junctions of the latch as well as the input junctions /JTLIN/J2 and /JTLCLK/J2. Here's the test sequence (programmed with PSCAN's internal function PULS1) and this is the SQHDL description of the latch.

Layout

This version was part of the autocorrelator shift register design laid out for fabrication by Hypres, Inc. Layout size is 110x60 um2.
The D flip-flop is formed by junctions JDA1 (=J1 in the above schematic), JDA2 (J2) and JDA3 (J3).

And here's an actual micro-photograph of the design:

References

The device is very similar to the one described in:

O. A. Mukhanov, V. K. Semenov, and K. K. Likharev, "Ultimate performance of the RSFQ Logic Circuits," IEEE Trans. Magn., vol. MAG-23, No. 2, pp. 759-762, Mar. 1987.
K. Likharev and V. Semenov, "RSFQ logic/memory family: A new josephson-junction technology for sub-terahertz clock-frequency digital systems", IEEE Trans. Appl. Supercond., vol. 1, pp. 3-28, March 1991.

Additionally, a somewhat outdated info is contained in A. Rylyakov's online thesis .

Send comments to A. Rylyakov sasha@rsfq1.physics.sunysb.edu

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